![]() Since the simulation also accounts for communication delays between the LabVIEW host interface and the FPGA, the start delay also ensures that in the simulation the written data has been loaded on the registers before the Add functions are allowed to execute. A sequence structure encapsulates the loops in order to control when the loop execution starts, and the start Boolean triggers the test. This VI benchmarks the execution time difference between using an Add function in a normal while loop versus a single-cycle timed loop (SCTL).Īs show in Figure 3 below, each loop contains an Add function and an indicator. ![]() Refer to the target hardware documentation for information about simulation support.Īdd a new VI under the PXI-7854R target and name the VI FPGA Add Test.vi.įigure 2. Add the FPGA target and a New VI Note: Support for cycle-accurate simulation varies by FPGA target. For this example, use an NI PXI-7854R R Series Multifunction RIO device. The target should support LabVIEW FPGA simulation. Note: If you use the attached lv_fpga_isim_ex project files, you can skip this section.Ĭreate a LabVIEW project and save the project as LV FPGA ISim Example.lvproj. The simulation example will compare an Add function executing in a normal versus a single-cycle timed loop in a LabVIEW FPGA VI.įirst, create a new LabVIEW FPGA project and an FPGA VI to test in ISim. ![]()
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